#include <stdio.h>

#define HIETH_SYSREG_BASE	(0x101e0000)
#define REG_RESET	0x01C	// 外设控制寄存器(IP软复位控制)
#define RESET_SHIFT	12


static void hieth_set_regbit(unsigned long addr, int bit, int shift)
{
	unsigned long reg;

	reg = 0xffffffff;

	bit = bit ? 1 : 0;
	printf("bit = %s\n", bit ? "Ture" : "Flase");

	reg &= ~(1 << shift);
	printf("reg & = %lx\n", reg);
	reg |= bit << shift;
	printf("reg | = %lx\n", reg);

	reg = 0x00000000;

	bit = bit ? 1 : 0;
	printf("bit = %s\n", bit ? "Ture" : "Flase");

	reg &= ~(1 << shift);
	printf("reg & = %lx\n", reg);
	reg |= bit << shift;
	printf("reg | = %lx\n", reg);
}

typedef struct _DEF
{
	#define W	5
	int i;
}sdef;

void perfect()
{
	#define P	5
	printf("perfect = %d sizeof(sdef) = %ld\n", P, sizeof(sdef));
}

void perfect2()
{
	printf("perfect2 = %d\n", P);
}

#define MK_BITS(shift, nbits)	((((shift)&0x1f)<<16) | ((nbits)&0x1f))
#define BITS_RXPKG_RDY	MK_BITS(0,1)
#define hieth_readl_bits(ld, ofs, bits_desc) ({ \
		unsigned long _bits_desc = bits_desc; \
		unsigned long _shift = (_bits_desc)>>16; \
		unsigned long _mask = ((1<<(_bits_desc & 0x1F)) - 1)<<(_shift); \
		printf("[%ld %ld %ld]\n", _bits_desc, _shift, _mask);\
		printf("%ld\n", ((ld+ofs)&_mask)>>(_shift)); })

#define BITS_RXPKG_ID	MK_BITS(16, 6)

int main()
{
	int rst = 1;
	
	rst = !rst;
	printf("!rst = %d\n", rst);

	//hieth_set_regbit(HIETH_SYSREG_BASE + REG_RESET, 1, RESET_SHIFT);

	perfect();
	perfect2();

	//printf("%d shift(1>>16) = %d  %d  %d\n", MK_BITS(0,1), 1>>16, MK_BITS(16,6), MK_BITS(0,11));
	//printf("%d %d %d\n", MK_BITS(16,0), MK_BITS(17,0), MK_BITS(25,0));
	//printf("%d %d %d\n", 16 & 0x1f, 17 & 0x1f, 32 & 0x1f );
	printf("main   %d\n", hieth_readl_bits(0, 1, BITS_RXPKG_ID));	/* 此处的2为printf的返回值，意义是输出了2个字符 */

	return 0;
}

#if 0
/*
 * intel
 */


/*
 * arm v8
 */
static void hieth_set_regbit(unsigned long addr, int bit, int shift)
{
  400590:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400594:	910003fd 	mov	x29, sp
  400598:	f9000fa0 	str	x0, [x29, #24] ; addr
  40059c:	b90017a1 	str	w1, [x29, #20] ; bit
  4005a0:	b90013a2 	str	w2, [x29, #16] ; shift
	unsigned long reg;

	reg = 0xffffffff;
  4005a4:	b2407fe0 	mov	x0, #0xffffffff            	// #4294967295
  4005a8:	f90017a0 	str	x0, [x29, #40]              ; reg

	bit = bit ? 1 : 0;
  4005ac:	b94017a0 	ldr	w0, [x29, #20] ; bit
  4005b0:	7100001f 	cmp	w0, #0x0       ; Conditional Set, 相等设置为1，不等设置为0
  4005b4:	1a9f07e0 	cset	w0, ne  // ne = any
  4005b8:	53001c00 	uxtb	w0, w0
  4005bc:	b90017a0 	str	w0, [x29, #20]
	printf("bit = %s\n", bit ? "Ture" : "Flase");
  4005c0:	b94017a0 	ldr	w0, [x29, #20]
  4005c4:	7100001f 	cmp	w0, #0x0
  4005c8:	54000080 	b.eq	4005d8 <hieth_set_regbit+0x48>  // b.none
  4005cc:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  4005d0:	9122c000 	add	x0, x0, #0x8b0
  4005d4:	14000003 	b	4005e0 <hieth_set_regbit+0x50>
  4005d8:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  4005dc:	9122e000 	add	x0, x0, #0x8b8
  4005e0:	90000001 	adrp	x1, 400000 <_init-0x3c8>
  4005e4:	91230022 	add	x2, x1, #0x8c0
  4005e8:	aa0003e1 	mov	x1, x0
  4005ec:	aa0203e0 	mov	x0, x2
  4005f0:	97ffff90 	bl	400430 <printf@plt>

	reg &= ~(1 << shift);
  4005f4:	b94013a0 	ldr	w0, [x29, #16]
  4005f8:	52800021 	mov	w1, #0x1                   	// #1
  4005fc:	1ac02020 	lsl	w0, w1, w0
  400600:	2a2003e0 	mvn	w0, w0
  400604:	93407c00 	sxtw	x0, w0
  400608:	f94017a1 	ldr	x1, [x29, #40]
  40060c:	8a000020 	and	x0, x1, x0
  400610:	f90017a0 	str	x0, [x29, #40]
	printf("reg & = %lx\n", reg);
  400614:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  400618:	91234000 	add	x0, x0, #0x8d0
  40061c:	f94017a1 	ldr	x1, [x29, #40]
  400620:	97ffff84 	bl	400430 <printf@plt>
	reg |= bit << shift;
  400624:	b94013a0 	ldr	w0, [x29, #16]
  400628:	b94017a1 	ldr	w1, [x29, #20]
  40062c:	1ac02020 	lsl	w0, w1, w0
  400630:	93407c00 	sxtw	x0, w0
  400634:	f94017a1 	ldr	x1, [x29, #40]
  400638:	aa000020 	orr	x0, x1, x0
  40063c:	f90017a0 	str	x0, [x29, #40]
	printf("reg | = %lx\n", reg);
  400640:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  400644:	91238000 	add	x0, x0, #0x8e0
  400648:	f94017a1 	ldr	x1, [x29, #40]
  40064c:	97ffff79 	bl	400430 <printf@plt>

	reg = 0x00000000;
  400650:	f90017bf 	str	xzr, [x29, #40]

	bit = bit ? 1 : 0;
  400654:	b94017a0 	ldr	w0, [x29, #20]
  400658:	7100001f 	cmp	w0, #0x0
  40065c:	1a9f07e0 	cset	w0, ne  // ne = any Conditional Set, 相等设置为1，不等设置为0
  400660:	53001c00 	uxtb	w0, w0
  400664:	b90017a0 	str	w0, [x29, #20]
	printf("bit = %s\n", bit ? "Ture" : "Flase");
  400668:	b94017a0 	ldr	w0, [x29, #20]
  40066c:	7100001f 	cmp	w0, #0x0
  400670:	54000080 	b.eq	400680 <hieth_set_regbit+0xf0>  // b.none
  400674:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  400678:	9122c000 	add	x0, x0, #0x8b0
  40067c:	14000003 	b	400688 <hieth_set_regbit+0xf8>
  400680:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  400684:	9122e000 	add	x0, x0, #0x8b8
  400688:	90000001 	adrp	x1, 400000 <_init-0x3c8>
  40068c:	91230022 	add	x2, x1, #0x8c0
  400690:	aa0003e1 	mov	x1, x0
  400694:	aa0203e0 	mov	x0, x2
  400698:	97ffff66 	bl	400430 <printf@plt>

	reg &= ~(1 << shift);
  40069c:	b94013a0 	ldr	w0, [x29, #16]
  4006a0:	52800021 	mov	w1, #0x1                   	// #1
  4006a4:	1ac02020 	lsl	w0, w1, w0
  4006a8:	2a2003e0 	mvn	w0, w0
  4006ac:	93407c00 	sxtw	x0, w0
  4006b0:	f94017a1 	ldr	x1, [x29, #40]
  4006b4:	8a000020 	and	x0, x1, x0
  4006b8:	f90017a0 	str	x0, [x29, #40]
	printf("reg & = %lx\n", reg);
  4006bc:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  4006c0:	91234000 	add	x0, x0, #0x8d0
  4006c4:	f94017a1 	ldr	x1, [x29, #40]
  4006c8:	97ffff5a 	bl	400430 <printf@plt>
	reg |= bit << shift;
  4006cc:	b94013a0 	ldr	w0, [x29, #16]
  4006d0:	b94017a1 	ldr	w1, [x29, #20]
  4006d4:	1ac02020 	lsl	w0, w1, w0
  4006d8:	93407c00 	sxtw	x0, w0
  4006dc:	f94017a1 	ldr	x1, [x29, #40]
  4006e0:	aa000020 	orr	x0, x1, x0
  4006e4:	f90017a0 	str	x0, [x29, #40]
	printf("reg | = %lx\n", reg);
  4006e8:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  4006ec:	91238000 	add	x0, x0, #0x8e0
  4006f0:	f94017a1 	ldr	x1, [x29, #40]
  4006f4:	97ffff4f 	bl	400430 <printf@plt>
}
  4006f8:	d503201f 	nop
  4006fc:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400700:	d65f03c0 	ret

0000000000400704 <perfect>:
	#define W	5
	int i;
}sdef;

void perfect()
{
  400704:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400708:	910003fd 	mov	x29, sp
	#define P	5
	printf("perfect = %d sizeof(sdef) = %d\n", P, sizeof(sdef));
  40070c:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  400710:	9123c000 	add	x0, x0, #0x8f0
  400714:	d2800082 	mov	x2, #0x4                   	// #4
  400718:	528000a1 	mov	w1, #0x5                   	// #5
  40071c:	97ffff45 	bl	400430 <printf@plt>
}
  400720:	d503201f 	nop
  400724:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400728:	d65f03c0 	ret

000000000040072c <perfect2>:

void perfect2()
{
  40072c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400730:	910003fd 	mov	x29, sp
	printf("perfect2 = %d\n", P);
  400734:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  400738:	91244000 	add	x0, x0, #0x910
  40073c:	528000a1 	mov	w1, #0x5                   	// #5
  400740:	97ffff3c 	bl	400430 <printf@plt>
}
  400744:	d503201f 	nop
  400748:	a8c17bfd 	ldp	x29, x30, [sp], #16
  40074c:	d65f03c0 	ret

0000000000400750 <main>:
		printf("%d\n", ((ld+ofs)&_mask)>>(_shift)); })

#define BITS_RXPKG_ID	MK_BITS(16, 6)

int main()
{
  400750:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400754:	910003fd 	mov	x29, sp
	int rst = 1;
  400758:	52800020 	mov	w0, #0x1                   	// #1
  40075c:	b9002fa0 	str	w0, [x29, #44]
	
	rst = !rst;
  400760:	b9402fa0 	ldr	w0, [x29, #44]
  400764:	7100001f 	cmp	w0, #0x0
  400768:	1a9f17e0 	cset	w0, eq  // eq = none
  40076c:	53001c00 	uxtb	w0, w0
  400770:	b9002fa0 	str	w0, [x29, #44]
	printf("!rst = %d\n", rst);
  400774:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  400778:	91248000 	add	x0, x0, #0x920
  40077c:	b9402fa1 	ldr	w1, [x29, #44]
  400780:	97ffff2c 	bl	400430 <printf@plt>

	//hieth_set_regbit(HIETH_SYSREG_BASE + REG_RESET, 1, RESET_SHIFT);

	perfect();
  400784:	97ffffe0 	bl	400704 <perfect>
	perfect2();
  400788:	97ffffe9 	bl	40072c <perfect2>

	//printf("%d shift(1>>16) = %d  %d  %d\n", MK_BITS(0,1), 1>>16, MK_BITS(16,6), MK_BITS(0,11));
	//printf("%d %d %d\n", MK_BITS(16,0), MK_BITS(17,0), MK_BITS(25,0));
	//printf("%d %d %d\n", 16 & 0x1f, 17 & 0x1f, 32 & 0x1f );
	printf("main   %d\n", hieth_readl_bits(0, 1, BITS_RXPKG_ID));
  40078c:	d28000c0 	mov	x0, #0x6                   	// #6
  400790:	f2a00200 	movk	x0, #0x10, lsl #16
  400794:	f90013a0 	str	x0, [x29, #32]
  400798:	f94013a0 	ldr	x0, [x29, #32]
  40079c:	d350fc00 	lsr	x0, x0, #16
  4007a0:	f9000fa0 	str	x0, [x29, #24]
  4007a4:	f94013a0 	ldr	x0, [x29, #32]
  4007a8:	12001000 	and	w0, w0, #0x1f
  4007ac:	52800021 	mov	w1, #0x1                   	// #1
  4007b0:	1ac02020 	lsl	w0, w1, w0
  4007b4:	51000400 	sub	w0, w0, #0x1
  4007b8:	f9400fa1 	ldr	x1, [x29, #24]
  4007bc:	1ac12000 	lsl	w0, w0, w1
  4007c0:	93407c00 	sxtw	x0, w0
  4007c4:	f9000ba0 	str	x0, [x29, #16]
  4007c8:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  4007cc:	9124c000 	add	x0, x0, #0x930
  4007d0:	f9400ba3 	ldr	x3, [x29, #16]
  4007d4:	f9400fa2 	ldr	x2, [x29, #24]
  4007d8:	f94013a1 	ldr	x1, [x29, #32]
  4007dc:	97ffff15 	bl	400430 <printf@plt>
  4007e0:	f9400ba0 	ldr	x0, [x29, #16]
  4007e4:	92400000 	and	x0, x0, #0x1
  4007e8:	f9400fa1 	ldr	x1, [x29, #24]
  4007ec:	9ac12401 	lsr	x1, x0, x1
  4007f0:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  4007f4:	91250000 	add	x0, x0, #0x940
  4007f8:	97ffff0e 	bl	400430 <printf@plt>
  4007fc:	2a0003e1 	mov	w1, w0
  400800:	90000000 	adrp	x0, 400000 <_init-0x3c8>
  400804:	91252000 	add	x0, x0, #0x948
  400808:	97ffff0a 	bl	400430 <printf@plt>

	return 0;
  40080c:	52800000 	mov	w0, #0x0                   	// #0
}

/*
 * arm v7
 */
static void hieth_set_regbit(unsigned long addr, int bit, int shift)
{
   10490:	e92d4800 	push	{fp, lr}
   10494:	e28db004 	add	fp, sp, #4
   10498:	e24dd018 	sub	sp, sp, #24
   1049c:	e50b0010 	str	r0, [fp, #-16] ; addr
   104a0:	e50b1014 	str	r1, [fp, #-20]	; 0xffffffec    bit
   104a4:	e50b2018 	str	r2, [fp, #-24]	; 0xffffffe8    shift
	unsigned long reg;

	reg = 0xffffffff;
   104a8:	e3e03000 	mvn	r3, #0
   104ac:	e50b3008 	str	r3, [fp, #-8] ; reg

	bit = bit ? 1 : 0;
   104b0:	e51b3014 	ldr	r3, [fp, #-20]	; 0xffffffec    bit
   104b4:	e3530000 	cmp	r3, #0
   104b8:	13a03001 	movne	r3, #1 ; ne ---> 1
   104bc:	03a03000 	moveq	r3, #0 ; eq ---> 0
   104c0:	e20330ff 	and	r3, r3, #255	; 0xff  r3 = (1|0)&0xff
   104c4:	e50b3014 	str	r3, [fp, #-20]	; 0xffffffec    save bit
	printf("bit = %s\n", bit ? "Ture" : "Flase");
   104c8:	e51b3014 	ldr	r3, [fp, #-20]	; 0xffffffec
   104cc:	e3530000 	cmp	r3, #0
   104d0:	0a000001 	beq	104dc <hieth_set_regbit+0x4c>
   104d4:	e59f3104 	ldr	r3, [pc, #260]	; 105e0 <hieth_set_regbit+0x150>
   104d8:	ea000000 	b	104e0 <hieth_set_regbit+0x50>
   104dc:	e59f3100 	ldr	r3, [pc, #256]	; 105e4 <hieth_set_regbit+0x154>
   104e0:	e1a01003 	mov	r1, r3
   104e4:	e59f00fc 	ldr	r0, [pc, #252]	; 105e8 <hieth_set_regbit+0x158>
   104e8:	ebffff88 	bl	10310 <printf@plt>

	reg &= ~(1 << shift);
   104ec:	e3a02001 	mov	r2, #1         ; r2 = 1
   104f0:	e51b3018 	ldr	r3, [fp, #-24]	; 0xffffffe8 shift
   104f4:	e1a03312 	lsl	r3, r2, r3      ; r3 = 1 << shift
   104f8:	e1e03003 	mvn	r3, r3          ; ~(1<<shift)
   104fc:	e1a02003 	mov	r2, r3          ; r2 = ~(1<<shift)
   10500:	e51b3008 	ldr	r3, [fp, #-8]   ; r3 = reg
   10504:	e0033002 	and	r3, r3, r2      ; r3 = reg & ~(1<<shift)
   10508:	e50b3008 	str	r3, [fp, #-8]   ; reg
	printf("reg & = %lx\n", reg);
   1050c:	e51b1008 	ldr	r1, [fp, #-8] ; reg
   10510:	e59f00d4 	ldr	r0, [pc, #212]	; 105ec <hieth_set_regbit+0x15c>
   10514:	ebffff7d 	bl	10310 <printf@plt>
	reg |= bit << shift;
   10518:	e51b2014 	ldr	r2, [fp, #-20]	; 0xffffffec    bit
   1051c:	e51b3018 	ldr	r3, [fp, #-24]	; 0xffffffe8    shift
   10520:	e1a03312 	lsl	r3, r2, r3      ; r3 = bit << shift
   10524:	e1a02003 	mov	r2, r3          ; r2 = bit << shift
   10528:	e51b3008 	ldr	r3, [fp, #-8]   ; reg
   1052c:	e1833002 	orr	r3, r3, r2      ; r3 = reg | (bit << shift)
   10530:	e50b3008 	str	r3, [fp, #-8]   ; save reg
	printf("reg | = %lx\n", reg);
   10534:	e51b1008 	ldr	r1, [fp, #-8] ; reg
   10538:	e59f00b0 	ldr	r0, [pc, #176]	; 105f0 <hieth_set_regbit+0x160>
   1053c:	ebffff73 	bl	10310 <printf@plt>

	reg = 0x00000000;
   10540:	e3a03000 	mov	r3, #0
   10544:	e50b3008 	str	r3, [fp, #-8]

	bit = bit ? 1 : 0;
   10548:	e51b3014 	ldr	r3, [fp, #-20]	; 0xffffffec    bit
   1054c:	e3530000 	cmp	r3, #0          ; ?= 0
   10550:	13a03001 	movne	r3, #1      ; ne ---> 1
   10554:	03a03000 	moveq	r3, #0      ; eq ---> 0
   10558:	e20330ff 	and	r3, r3, #255	; 0xff
   1055c:	e50b3014 	str	r3, [fp, #-20]	; 0xffffffec
	printf("bit = %s\n", bit ? "Ture" : "Flase");
   10560:	e51b3014 	ldr	r3, [fp, #-20]	; 0xffffffec
   10564:	e3530000 	cmp	r3, #0
   10568:	0a000001 	beq	10574 <hieth_set_regbit+0xe4>
   1056c:	e59f306c 	ldr	r3, [pc, #108]	; 105e0 <hieth_set_regbit+0x150>
   10570:	ea000000 	b	10578 <hieth_set_regbit+0xe8>
   10574:	e59f3068 	ldr	r3, [pc, #104]	; 105e4 <hieth_set_regbit+0x154>
   10578:	e1a01003 	mov	r1, r3
   1057c:	e59f0064 	ldr	r0, [pc, #100]	; 105e8 <hieth_set_regbit+0x158>
   10580:	ebffff62 	bl	10310 <printf@plt>

	reg &= ~(1 << shift);
   10584:	e3a02001 	mov	r2, #1
   10588:	e51b3018 	ldr	r3, [fp, #-24]	; 0xffffffe8
   1058c:	e1a03312 	lsl	r3, r2, r3
   10590:	e1e03003 	mvn	r3, r3
   10594:	e1a02003 	mov	r2, r3
   10598:	e51b3008 	ldr	r3, [fp, #-8]
   1059c:	e0033002 	and	r3, r3, r2
   105a0:	e50b3008 	str	r3, [fp, #-8]
	printf("reg & = %lx\n", reg);
   105a4:	e51b1008 	ldr	r1, [fp, #-8]
   105a8:	e59f003c 	ldr	r0, [pc, #60]	; 105ec <hieth_set_regbit+0x15c>
   105ac:	ebffff57 	bl	10310 <printf@plt>
	reg |= bit << shift;
   105b0:	e51b2014 	ldr	r2, [fp, #-20]	; 0xffffffec
   105b4:	e51b3018 	ldr	r3, [fp, #-24]	; 0xffffffe8
   105b8:	e1a03312 	lsl	r3, r2, r3
   105bc:	e1a02003 	mov	r2, r3
   105c0:	e51b3008 	ldr	r3, [fp, #-8]
   105c4:	e1833002 	orr	r3, r3, r2
   105c8:	e50b3008 	str	r3, [fp, #-8]
	printf("reg | = %lx\n", reg);
   105cc:	e51b1008 	ldr	r1, [fp, #-8]
   105d0:	e59f0018 	ldr	r0, [pc, #24]	; 105f0 <hieth_set_regbit+0x160>
   105d4:	ebffff4d 	bl	10310 <printf@plt>
}
   105d8:	e24bd004 	sub	sp, fp, #4
   105dc:	e8bd8800 	pop	{fp, pc}
   105e0:	00010718 	.word	0x00010718
   105e4:	00010720 	.word	0x00010720
   105e8:	00010728 	.word	0x00010728
   105ec:	00010734 	.word	0x00010734
   105f0:	00010744 	.word	0x00010744

000105f4 <perfect>:
	#define W	5
	int i;
}sdef;

void perfect()
{
   105f4:	e92d4800 	push	{fp, lr}
   105f8:	e28db004 	add	fp, sp, #4
	#define P	5
	printf("perfect = %d sizeof(sdef) = %d\n", P, sizeof(sdef));
   105fc:	e3a02004 	mov	r2, #4
   10600:	e3a01005 	mov	r1, #5
   10604:	e59f0004 	ldr	r0, [pc, #4]	; 10610 <perfect+0x1c>
   10608:	ebffff40 	bl	10310 <printf@plt>
}
   1060c:	e8bd8800 	pop	{fp, pc}
   10610:	00010754 	.word	0x00010754

00010614 <perfect2>:

void perfect2()
{
   10614:	e92d4800 	push	{fp, lr}
   10618:	e28db004 	add	fp, sp, #4
	printf("perfect2 = %d\n", P);
   1061c:	e3a01005 	mov	r1, #5
   10620:	e59f0004 	ldr	r0, [pc, #4]	; 1062c <perfect2+0x18>
   10624:	ebffff39 	bl	10310 <printf@plt>
}
   10628:	e8bd8800 	pop	{fp, pc}
   1062c:	00010774 	.word	0x00010774

00010630 <main>:
		printf("%d\n", ((ld+ofs)&_mask)>>(_shift)); })

#define BITS_RXPKG_ID	MK_BITS(16, 6)

int main()
{
   10630:	e92d4800 	push	{fp, lr}
   10634:	e28db004 	add	fp, sp, #4
   10638:	e24dd010 	sub	sp, sp, #16
	int rst = 1;
   1063c:	e3a03001 	mov	r3, #1
   10640:	e50b3008 	str	r3, [fp, #-8] ; rst
	
	rst = !rst;
   10644:	e51b3008 	ldr	r3, [fp, #-8] ; rst
   10648:	e3530000 	cmp	r3, #0        ; =? 0
   1064c:	03a03001 	moveq	r3, #1    ; eq ---> 1
   10650:	13a03000 	movne	r3, #0    ; ne ---> 0
   10654:	e20330ff 	and	r3, r3, #255	; 0xff
   10658:	e50b3008 	str	r3, [fp, #-8]
	printf("!rst = %d\n", rst);
   1065c:	e51b1008 	ldr	r1, [fp, #-8]
   10660:	e59f008c 	ldr	r0, [pc, #140]	; 106f4 <main+0xc4>
   10664:	ebffff29 	bl	10310 <printf@plt>

	//hieth_set_regbit(HIETH_SYSREG_BASE + REG_RESET, 1, RESET_SHIFT);

	perfect();
   10668:	ebffffe1 	bl	105f4 <perfect>
	perfect2();
   1066c:	ebffffe8 	bl	10614 <perfect2>

	//printf("%d shift(1>>16) = %d  %d  %d\n", MK_BITS(0,1), 1>>16, MK_BITS(16,6), MK_BITS(0,11));
	//printf("%d %d %d\n", MK_BITS(16,0), MK_BITS(17,0), MK_BITS(25,0));
	//printf("%d %d %d\n", 16 & 0x1f, 17 & 0x1f, 32 & 0x1f );
	printf("main   %d\n", hieth_readl_bits(0, 1, BITS_RXPKG_ID));
   10670:	e59f3080 	ldr	r3, [pc, #128]	; 106f8 <main+0xc8>
   10674:	e50b300c 	str	r3, [fp, #-12]
   10678:	e51b300c 	ldr	r3, [fp, #-12]
   1067c:	e1a03823 	lsr	r3, r3, #16
   10680:	e50b3010 	str	r3, [fp, #-16]
   10684:	e51b300c 	ldr	r3, [fp, #-12]
   10688:	e203301f 	and	r3, r3, #31
   1068c:	e3a02001 	mov	r2, #1
   10690:	e1a03312 	lsl	r3, r2, r3
   10694:	e2432001 	sub	r2, r3, #1
   10698:	e51b3010 	ldr	r3, [fp, #-16]
   1069c:	e1a03312 	lsl	r3, r2, r3
   106a0:	e50b3014 	str	r3, [fp, #-20]	; 0xffffffec
   106a4:	e51b3014 	ldr	r3, [fp, #-20]	; 0xffffffec
   106a8:	e51b2010 	ldr	r2, [fp, #-16]
   106ac:	e51b100c 	ldr	r1, [fp, #-12]
   106b0:	e59f0044 	ldr	r0, [pc, #68]	; 106fc <main+0xcc>
   106b4:	ebffff15 	bl	10310 <printf@plt>
   106b8:	e51b3014 	ldr	r3, [fp, #-20]	; 0xffffffec
   106bc:	e2032001 	and	r2, r3, #1
   106c0:	e51b3010 	ldr	r3, [fp, #-16]
   106c4:	e1a03332 	lsr	r3, r2, r3
   106c8:	e1a01003 	mov	r1, r3
   106cc:	e59f002c 	ldr	r0, [pc, #44]	; 10700 <main+0xd0>
   106d0:	ebffff0e 	bl	10310 <printf@plt>
   106d4:	e1a03000 	mov	r3, r0
   106d8:	e1a01003 	mov	r1, r3
   106dc:	e59f0020 	ldr	r0, [pc, #32]	; 10704 <main+0xd4>
   106e0:	ebffff0a 	bl	10310 <printf@plt>

	return 0;
   106e4:	e3a03000 	mov	r3, #0
}

#endif